This invention relates to an improved field-effect transistor (FET) and especially to improvement of FET's by tailoring the source-gate channel resistivity to be high in the upper layer and lower in the lower layer.
Transconductance, gate capacitance, source parasitics, and source-gate channel resistance are the factors universally known to affect the performance of field-effect transistors. Previous work in the field has done much to improve transconductance by improving materials' quality and materials' interfaces. Gate capacitance has been reduced by using submicrometer resolution lithography. Source parasitics have been greatly reduced by better metallization for ohmic contacts by "via" technology and by monolithic, Class B, push-pull circuit techniques. Only source-gate channel resistance has evaded a solution enabling it to be reduced without adversely affecting gate leakage characteristics.